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1. general description the lpc2131/2132/2138 microcontrollers are based on a 32/16 bit arm7tdmi-s? cpu with real-time emulation and embedded trace support, that combines the microcontroller with 32 kb, 64 kb and 512 kb of embedded high speed flash memory. a 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. for critical code size applications, the alternative 16-bit thumb ? mode reduces code by more than 30 % with minimal performance penalty. due to their tiny size and low power consumption, these microcontrollers are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. with a wide range of serial communications interfaces and on-chip sram options of 8/16/32 kb, they are very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. various 32-bit timers, single or dual 10-bit 8 channel adc(s), 10-bit dac, pwm channels and 47 gpio lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems. 2. features 2.1 key features n 16/32-bit arm7tdmi-s microcontroller in a tiny lqfp64 package. n 8/16/32 kb of on-chip static ram and 64/512 kb of on-chip flash program memory. 128 bit wide interface/accelerator enables high speed 60 mhz operation. n in-system/in-application programming (isp/iap) via on-chip boot-loader software. single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms. n embeddedice ? rt and embedded trace interfaces offer real-time debugging with the on-chip realmonitor? software and high speed tracing of instruction execution. n one (lpc2131/2132) or two (lpc2138) 8 channel 10-bit a/d converters provides a total of up to 16 analog inputs, with conversion times as low as 2.44 m s per channel. n single 10-bit d/a converter provides variable analog output. (lpc2132/2138 only) n two 32-bit timers/counters (with four capture and four compare channels each), pwm unit (six outputs) and watchdog. n real-time clock equipped with independent power and clock supply permitting extremely low power consumption in power-save modes. n multiple serial interfaces including two uarts (16c550), two fast i 2 c-bus (400 kbit/s), spi? and ssp with buffering and variable data length capabilities. n vectored interrupt controller with con?gurable priorities and vector addresses. lpc2131/2132/2138 single-chip 16/32-bit microcontrollers; 32/64/512 kb isp/iap flash with 10-bit adc and dac rev. 01 18 november 2004 preliminary data sheet
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 2 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers n up to 47 5 v tolerant general purpose i/o pins in tiny lqfp64 package. n up to nine edge or level sensitive external interrupt pins available. n 60 mhz maximum cpu clock available from programmable on-chip pll with settling time of 100 m s. n on-chip crystal oscillator with an operating range of 1 mhz to 30 mhz. n power saving modes include idle and power-down. n individual enable/disable of peripheral functions as well as peripheral clock scaling down for additional power optimization. n processor wake-up from power-down mode via external interrupt. n single power supply chip with por and bod circuits: u cpu operating voltage range of 3.0 v to 3.6 v (3.3 v 10 %) with 5 v tolerant i/o pads. 3. ordering information 3.1 ordering options table 1: ordering information type number package name description version LPC2131FBD64 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 lpc2132fbd64 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 lpc2138fbd64 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 table 2: ordering options type number flash memory ram can temperature range ( c) LPC2131FBD64 32 kb 8 kb - - 40 to +85 lpc2132fbd64 64 kb 16 kb - - 40 to +85 lpc2138fbd64 512 kb 32 kb - - 40 to +85
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 3 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 4. block diagram (1) lpc2138 only. (2) lpc2132/2138 only. fig 1. block diagram. 002aab067 system clock scl0,1 aout (2) p0.31:0 p1.31:16, 1:0 sda0,1 trst (1) tms (1) tck (1) tdi (1) tdo (1) xtal2 xtal1 sck0,1 mosi0,1 miso0,1 eint3:0 8 cap0 8 mat ad0.7:0 ad1.7:0 (1) pwm6:1 ssel0,1 txd0,1 rxd0,1 rtxc2 rtxc1 v bat dsr1 (1) ,cts1 (1) , rts1 (1) , dtr1 (1) dcd1 (1) ,ri1 (1) amba ahb (advanced high-performance bus) internal flash controller ahb bridge emulation trace module test/debug interface ahb decoder ahb to vpb bridge vpb divider vectored interrupt controller system functions pll spi and ssp serial interfaces i 2 c serial interfaces 0 and 1 uart0/uart1 real time clock watchdog timer system control external interrupts general purpose i/o pwm0 capture/ compare timer 0/timer 1 a/d converters 0 and 1 (1) d/a converter (2) 32/64/512 kb flash arm7tdmi-s lpc2132/2138 internal sram controller 8/16/32 kb sram arm7 local bus vpb (vlsi peripheral bus) rst
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 4 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 5. pinning information 5.1 pinning (1) lpc2138 only. (2) lpc2132/2138 only. fig 2. pinning. lpc2131/2132/2138 p0.21/pwm5/ad1.6 (1) /cap1.3 p1.20/tracesync p0.22/ad1.7 (1) /cap0.0/mat0.0 p0.17/cap1.2/sck1/mat1.2 rtxc1 p0.16/eint0/mat0.2/cap0.2 p1.19/tracepkt3 p0.15/ri1 (1) /eint2/ad1.5 (1) rtxc2 p1.21/pipestat0 v ss v dd v dda v ss p1.18/tracepkt2 p0.14/dcd1 (1) /eint1/sda1 p0.25/ad0.4/aout (2) p1.22/pipestat1 p0.26/ad0.5 p0.13/dtr1 (1) /mat1.1/ad1.4 (1) p0.27/ad0.0/cap0.1/mat0.1 p0.12/dsr1 (1) /mat1.0/ad1.3 (1) p1.17/tracepkt1 p0.11/cts1 (1) /cap1.1/scl1 p0.28/ad0.1/cap0.2/mat0.2 p1.23/pipestat2 p0.29/ad0.2/cap0.3/mat0.3 p0.10/rts1 (1) /cap1.0/ad1.2 (1) p0.30/ad0.3/eint3/cap0.0 p0.9/rxd1/pwm6/eint3 p1.16/tracepkt0 p0.8/txd1/pwm4/ad1.1 (1) p0.31 p1.27/tdo v ss v ref p0.0/txd0/pwm1 xtal1 p1.31/trst xtal2 p0.1/rxd0/pwm3/eint0 p1.28/tdi p0.2/scl0/cap0.0 v ssa v dd p0.23 p1.26/rtck reset v ss p1.29/tck p0.3/sda0/mat0.0/eint1 p0.20/mat1.3/ssel1/eint3 p0.4/sck0/cap0.1/ad0.6 p0.19/mat1.2/mosi1/cap1.2 p1.25/extin0 p0.18/cap1.3/miso1/mat1.3 p0.5/miso0/mat0.1/ad0.7 p1.30/tms p0.6/mosi0/cap0.2/ad1.0 (1) v dd p0.7/ssel0/pwm2/eint2 v ss p1.24/traceclk v bat 002aab068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 5 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 5.2 pin description table 3: pin description symbol pin type description p0.0 to p0.31 i/o port 0: port 0 is a 32-bit i/o port with individual direction controls for each bit. total of 31 pins of the port 0 can be used as a general purpose bi-directional digital i/os while p0.31 is output only pin. the operation of port 0 pins depends upon the pin function selected via the pin connect block. pin p0.24 is not available. p0.0/txd0/ pwm1 19 o txd0 transmitter output for uart0. o pwm1 pulse width modulator output 1. p0.1/rxd0/ pwm3/eint0 21 i rxd0 receiver input for uart0. o pwm3 pulse width modulator output 3. i eint0 external interrupt 0 input p0.2/scl0/ cap0.0 22 i/o scl0 i 2 c0 clock input/output. open drain output (for i 2 c-bus compliance). i cap0.0 capture input for timer 0, channel 0. p0.3/sda0/ mat0.0/eint1 26 i/o sda0 i 2 c0 data input/output. open drain output (for i 2 c-bus compliance). o mat0.0 match output for timer 0, channel 0. i eint1 external interrupt 1 input. p0.4/sck0/ cap0.1/ad0.6 27 i/o sck0 serial clock for spi0. spi clock output from master or input to slave. i cap0.1 capture input for timer 0, channel 0. i ad0.6 a/d converter 0, input 6. this analog input is always connected to its pin. p0.5/miso0/ mat0.1/ad0.7 29 i/o miso0 master in slave out for spi0. data input to spi master or data output from spi slave. o mat0.1 match output for timer 0, channel 1. i ad0.7 a/d converter 0, input 7. this analog input is always connected to its pin. p0.6/mosi0/ cap0.2/ad1.0 30 i/o mosi0 master out slave in for spi0. data output from spi master or data input to spi slave. i cap0.2 capture input for timer 0, channel 2. i ad1.0 a/d converter 1, input 0. this analog input is always connected to its pin. available in lpc2138 only. p0.7/ssel0/ pwm2/eint2 31 i ssel0 slave select for spi0. selects the spi interface as a slave. o pwm2 pulse width modulator output 2. i eint2 external interrupt 2 input. p0.8/txd1/ pwm4/ad1.1 33 o txd1 transmitter output for uart1. o pwm4 pulse width modulator output 4. i ad1.1 a/d converter 1, input 1. this analog input is always connected to its pin. available in lpc2138 only. p0.9/rxd1/ pwm6/eint3 34 i rxd1 receiver input for uart1. o pwm6 pulse width modulator output 6. i eint3 external interrupt 3 input.
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 6 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers p0.10/rts1/ cap1.0/ad1.2 35 o rts1 request to send output for uart1. available in lpc2138 only. i cap1.0 capture input for timer 1, channel 0. i ad1.2 a/d converter 1, input 2. this analog input is always connected to its pin. available in lpc2138 only. p0.11/cts1/ cap1.1/scl1 37 i cts1 clear to send input for uart1. available in lpc2138 only. i cap1.1 capture input for timer 1, channel 1. i/o scl1 i 2 c1 clock input/output. open drain output (for i 2 c-bus compliance) p0.12/dsr1/ mat1.0/ad1.3 38 i dsr1 data set ready input for uart1. available in lpc2138 only. o mat1.0 match output for timer 1, channel 0. i ad1.3 a/d converter input 3. this analog input is always connected to its pin. available in lpc2138 only. p0.13/dtr1/ mat1.1/ad1.4 39 o dtr1 data terminal ready output for uart1. available in lpc2138 only. o mat1.1 match output for timer 1, channel 1. i ad1.4 a/d converter input 4. this analog input is always connected to its pin. available in lpc2138 only. p0.14/dcd1/ eint1/sda1 41 i dcd1 data carrier detect input for uart1. available in lpc2138 only. i eint1 external interrupt 1 input. i/o sda1 i 2 c1 data input/output. open drain output (for i 2 c-bus compliance) p0.15/ri1/ eint2/ad1.5 45 i ri1 ring indicator input for uart1. available in lpc2138 only. i eint2 external interrupt 2 input. i ad1.5 a/d converter 1, input 5. this analog input is always connected to its pin. available in lpc2138 only. p0.16/eint0/ mat0.2/cap0.2 46 i eint0 external interrupt 0 input. o mat0.2 match output for timer 0, channel 2. i cap0.2 capture input for timer 0, channel 2. p0.17/cap1.2/ sck1/mat1.2 47 i cap1.2 capture input for timer 1, channel 2. i/o sck1 serial clock for ssp. clock output from master or input to slave. o mat1.2 match output for timer 1, channel 2. p0.18/cap1.3/ miso1/mat1.3 53 i cap1.3 capture input for timer 1, channel 3. i/o miso1 master in slave out for ssp. data input to spi master or data output from ssp slave. o mat1.3 match output for timer 1, channel 3. p0.19/mat1.2/ mosi1/cap1.2 54 o mat1.2 match output for timer 1, channel 2. i/o mosi1 master out slave in for ssp. data output from ssp master or data input to ssp slave. i cap1.2 capture input for timer 1, channel 2. p0.20/mat1.3/ ssel1/eint3 55 o mat1.3 match output for timer 1, channel 3. i ssel1 slave select for ssp. selects the ssp interface as a slave. i eint3 external interrupt 3 input. p0.21/pwm5/ ad1.6/cap1.3 1o pwm5 pulse width modulator output 5. i ad1.6 a/d converter 1, input 6. this analog input is always connected to its pin. available in lpc2138 only. i cap1.3 capture input for timer 1, channel 3. table 3: pin description continued symbol pin type description
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 7 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers p0.22/ad1.7/ cap0.0/mat0.0 2i ad1.7 a/d converter 1, input 7. this analog input is always connected to its pin. available in lpc2138 only. i cap0.0 capture input for timer 0, channel 0. o mat0.0 match output for timer 0, channel 0. p0.23 58 i/o general purpose digital input/output pin. p0.25/ad0.4/ aout 9i ad0.4 a/d converter 0, input 4. this analog input is always connected to its pin. o aout d/a converter output. available in lpc2132 and lpc2138 only. p0.26/ad0.5 10 i ad0.5 a/d converter 0, input 5. this analog input is always connected to its pin. p0.27/ad0.0/ cap0.1/mat0.1 11 i ad0.0 a/d converter 0, input 0. this analog input is always connected to its pin. i cap0.1 capture input for timer 0, channel 1. o mat0.1 match output for timer 0, channel 1. p0.28/ad0.1/ cap0.2/mat0.2 13 i ad0.1 a/d converter 0, input 1. this analog input is always connected to its pin. i cap0.2 capture input for timer 0, channel 2. o mat0.2 match output for timer 0, channel 2. p0.29/ad0.2/ cap0.3/mat0.3 14 i ad0.2 a/d converter 0, input 2. this analog input is always connected to its pin. i cap0.3 capture input for timer 0, channel 3. o mat0.3 match output for timer 0, channel 3. p0.30/ad0.3/ eint3/cap0.0 15 i ad0.3 a/d converter 0, input 3. this analog input is always connected to its pin. i eint3 external interrupt 3 input. i cap0.0 capture input for timer 0, channel 0. p0.31 17 o general purpose digital output only pin. p1.0 to p1.31 i/o port 1: port 1 is a 32-bit bi-directional i/o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block. pins 0 through 15 of port 1 are not available. p1.16/ tracepkt0 16 o tracepkt0 trace packet, bit 0. standard i/o port with internal pull-up. p1.17/ tracepkt1 12 o tracepkt1 trace packet, bit 1. standard i/o port with internal pull-up. p1.18/ tracepkt2 8o tracepkt2 trace packet, bit 2. standard i/o port with internal pull-up. p1.19/ tracepkt3 4o tracepkt3 trace packet, bit 3. standard i/o port with internal pull-up. p1.20/ tracesync 48 o tracesync trace synchronization. standard i/o port with internal pull-up. low on tracesync while reset is low enables pins p1.25:16 to operate as trace port after reset. p1.21/ pipestat0 44 o pipestat0 pipeline status, bit 0. standard i/o port with internal pull-up. p1.22/ pipestat1 40 o pipestat1 pipeline status, bit 1. standard i/o port with internal pull-up. table 3: pin description continued symbol pin type description
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 8 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers p1.23/ pipestat2 36 o pipestat2 pipeline status, bit 2. standard i/o port with internal pull-up. p1.24/ traceclk 32 o traceclk trace clock. standard i/o port with internal pull-up. p1.25/extin0 28 i extin0 external trigger input. standard i/o with internal pull-up. p1.26/rtck 24 i/o rtck returned test clock output. extra signal added to the jtag port. assists debugger synchronization when processor frequency varies. bi-directional pin with internal pull-up. low on rtck while reset is low enables pins p1.31:26 to operate as debug port after reset. p1.27/tdo 64 o tdo test data out for jtag interface. p1.28/tdi 60 i tdi test data in for jtag interface. p1.29/tck 56 i tck test clock for jtag interface. p1.30/tms 52 i tms test mode select for jtag interface. p1.31/ trst 20 i trst test reset for jtag interface. reset 57 i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. ttl with hysteresis, 5 v tolerant. xtal1 62 i input to the oscillator circuit and internal clock generator circuits. xtal2 61 o output from the oscillator ampli?er. rtxc1 3 i input to the rtc oscillator circuit. rtxc2 5 o output from the rtc oscillator circuit. v ss 6, 18, 25, 42, 50 i ground: 0 v reference. v ssa 59 i analog ground: 0 v reference. this should nominally be the same voltage as v ss , but should be isolated to minimize noise and error. v dd 23, 43, 51 i 3.3 v power supply: this is the power supply voltage for the core and i/o ports. v dda 7i analog 3.3 v power supply: this should be nominally the same voltage as v dd but should be isolated to minimize noise and error. this voltage is used to power the on-chip pll. v ref 63 i a/d converter reference: this should be nominally the same voltage as v dd but should be isolated to minimize noise and error. level on this pin is used as a reference for a/d convertor. v bat 49 i rtc power supply: 3.3 v on this pin supplies the power to the rtc. table 3: pin description continued symbol pin type description
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 9 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 6. functional description 6.1 architectural overview the arm7tdmi-s is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. the arm ? architecture is based on reduced instruction set computer (risc) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. this simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm7tdmi-s processor also employs a unique architectural strategy known as thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. the key idea behind thumb is that of a super-reduced instruction set. essentially, the arm7tdmi-s processor has two instruction sets: ? the standard 32-bit arm set. ? a 16-bit thumb set. the thumb sets 16-bit instruction length allows it to approach twice the density of standard arm code while retaining most of the arms performance advantage over a traditional 16-bit processor using 16-bit registers. this is possible because thumb code operates on the same 32-bit register set as arm code. thumb code is able to provide up to 65 % of the code size of arm, and 160 % of the performance of an equivalent arm processor connected to a 16-bit memory system. 6.2 on-chip flash program memory the lpc2131/2132/2138 incorporate a 32 kb, 64 kb and 512 kb flash memory system respectively. this memory may be used for both code and data storage. programming of the flash memory may be accomplished in several ways. it may be programmed in system via the serial port. the application program may also erase and/or program the flash while the application is running, allowing a great degree of ?exibility for data storage ?eld ?rmware upgrades, etc. when the lpc2131/2132/2138 on-chip bootloader is used, 32/64/500 kb of flash memory is available for user code. the lpc2131/2132/2138 flash memory provides minimum of 10,000 erase/write cycles and 10 years of data-retention. 6.3 on-chip static ram on-chip static ram may be used for code and/or data storage. the sram may be accessed as 8-bits, 16-bits, and 32-bits. the lpc2131/2132/2138 provide 8/16/32 kb of static ram.
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 10 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 6.4 memory map the lpc2131/2132/2138 memory maps incorporate several distinct regions, as shown in the following ?gures. in addition, the cpu interrupt vectors may be re-mapped to allow them to reside in either flash memory (the default) or on-chip static ram. this is described in section 6.21 system control . 6.5 interrupt controller the vic accepts all of the interrupt request inputs and categorizes them as fiq, vectored irq, and non-vectored irq as de?ned by programmable settings. the programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. fig 3. lpc2131/2132/2138 memory map. ahb peripherals vpb peripherals reserved address space boot block (re-mapped from on-chip flash memory reserved address space total of 64 kb on-chip static ram (lpc2138) total of 16 kb on-chip static ram (lpc2132) total of 8 kb on-chip static ram (lpc2131) total of 512 kb on-chip non-volatile memory (lpc2138) total of 64 kb on-chip non-volatile memory (lpc2132) total of 32 kb on-chip non-volatile memory (lpc2131) 0xffff ffff 0xf000 0000 0xe000 0000 0xc000 0000 0x8000 0000 0x4000 4000 0x4000 3fff 0x4000 2000 0x4000 1fff 0x4001 0000 0x4000 ffff 0x4000 0000 0x0001 0000 0x0000 ffff 0x0000 8000 0x0000 7fff 0x0008 0000 0x0007 ffff 0x0000 0000 4.0 gb 3.75 gb 3.5 gb 3.0 gb 2.0 gb 1.0 gb 0.0 gb 002aab069
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 11 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers fast interrupt request (fiq) has the highest priority. if more than one request is assigned to fiq, the vic combines the requests to produce the fiq signal to the arm processor. the fastest possible fiq latency is achieved when only one request is classi?ed as fiq, because then the fiq service routine can simply start dealing with that device. but if more than one request is assigned to the fiq class, the fiq service routine can read a word from the vic that identi?es which fiq source(s) is (are) requesting an interrupt. vectored irqs have the middle priority. sixteen of the interrupt requests can be assigned to this category. any of the interrupt requests can be assigned to any of the 16 vectored irq slots, among which slot 0 has the highest priority and slot 15 has the lowest. non-vectored irqs have the lowest priority. the vic combines the requests from all the vectored and non-vectored irqs to produce the irq signal to the arm processor. the irq service routine can start by reading a register from the vic and jumping there. if any of the vectored irqs are requesting, the vic provides the address of the highest-priority requesting irqs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored irqs. the default routine can read another vic register to see what irqs are active. 6.5.1 interrupt sources t ab le 4 lists the interrupt sources for each peripheral function. each peripheral device has one interrupt line connected to the vectored interrupt controller, but may have several internal interrupt ?ags. individual interrupt ?ags may also represent more than one interrupt source. table 4: interrupt sources block flag(s) vic channel # wdt watchdog interrupt (wdint) 0 - reserved for software interrupts only 1 arm core embedded ice, dbgcommrx 2 arm core embedded ice, dbgcommtx 3 timer0 match 0 to 3 (mr0, mr1, mr2, mr3) capture 0 to 3 (cr0, cr1, cr2, cr3) 4 timer1 match 0 to 3 (mr0, mr1, mr2, mr3) capture 0 to 3 (cr0, cr1, cr2, cr3) 5 uart0 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) 6 uart1 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) modem status interrupt (msi) (available in lpc2138 only) 7 pwm0 match 0 to 6 (mr0, mr1, mr2, mr3, mr4, mr5, mr6) capture 0 to 3 (cr0, cr1, cr2, cr3) 8 i 2 c0 si (state change) 9
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 12 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 6.6 pin connect block the pin connect block allows selected pins of the microcontroller to have more than one function. con?guration registers control the multiplexers to allow connection between the pin and the on chip peripherals. peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. activity of any enabled peripheral function that is not mapped to a related pin should be considered unde?ned. the pin control module contains three registers as shown in t ab le 5 . spi0 spif, modf 10 ssp tx fifo at least half empty (txris) rx fifo at least half full (rxris) receive timeout (rtris) receive overrun (rorris) 11 pll pll lock (plock) 12 rtc rtccif (counter increment), rtcalf (alarm) 13 system control external interrupt 0 (eint0) 14 external interrupt 1 (eint1) 15 external interrupt 2 (eint2) 16 external interrupt 3 (eint3) 17 ad0 a/d converter 0 18 i2c1 si (state change) 19 bod brown out detect 20 ad1 a/d converter 1 (available in lpc2138 only) 21 table 4: interrupt sources continued block flag(s) vic channel # table 5: pin control module registers address name description access 0xe002c000 pinsel0 pin function select register 0 read/write 0xe002c004 pinsel1 pin function select register 1 read/write 0xe002c014 pinsel2 pin function select register 2 read/write
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 13 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 6.7 pin function select register 0 (pinsel0 - 0xe002c000) the pinsel0 register controls the functions of the pins as per the settings listed in t ab le 6 . the direction control bit in the iodir register is effective only when the gpio function is selected for a pin. for other functions, direction is controlled automatically. settings other than those shown in t ab le 6 are reserved, and should not be used. table 6: pin function select register 0 (pinsel0 - 0xe002c000) pinsel0 pin name value function value after reset 1:0 p0.0 0 0 gpio port 0.0 0 0 1 txd (uart0) 1 0 pwm1 1 1 reserved 3:2 p0.1 0 0 gpio port 0.1 0 0 1 rxd (uart0) 1 0 pwm3 1 1 eint0 5:4 p0.2 0 0 gpio port 0.2 0 0 1 scl0 (i 2 c0) 1 0 capture 0.0 (timer 0) 1 1 reserved 7:6 p0.3 0 0 gpio port 0.3 0 0 1 sda0 (i 2 c0) 1 0 match 0.0 (timer 0) 1 1 eint1 9:8 p0.4 0 0 gpio port 0.4 0 0 1 sck0 (spi0) 1 0 capture 0.1 (timer 0) 1 1 ad0.6 11:10 p0.5 0 0 gpio port 0.5 0 0 1 miso0 (spi0) 1 0 match 0.1 (timer 0) 1 1 ad0.7 13:12 p0.6 0 0 gpio port 0.6 0 0 1 mosi0 (spi0) 1 0 capture 0.2 (timer 0) 1 1 reserved (lpc2131/32) ad1.0 (lpc2138) 15:14 p0.7 0 0 gpio port 0.7 0 0 1 ssel0 (spi0) 1 0 pwm2 1 1 eint2
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 14 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 17:16 p0.8 0 0 gpio port 0.8 0 0 1 txd uart1 1 0 pwm4 1 1 reserved (lpc2131/32) ad1.1 (lpc2138) 19:18 p0.9 0 0 gpio port 0.9 0 0 1 rxd (uart1) 1 0 pwm6 1 1 eint3 21:20 p0.10 0 0 gpio port 0.10 0 0 1 reserved (lpc2131/32) rts (uart1) (lpc2138) 1 0 capture 1.0 (timer 1) 1 1 reserved (lpc2131/32) ad1.2 (lpc2138) 23:22 p0.11 0 0 gpio port 0.11 0 0 1 reserved (lpc2131/32) cts (uart1) (lpc2138) 1 0 capture 1.1 (timer 1) 1 1 scl1 (i 2 c1) 25:24 p0.12 0 0 gpio port 0.12 0 0 1 reserved (lpc2131/32) dsr (uart1) (lpc2138) 1 0 match 1.0 (timer 1) 1 1 reserved (lpc2131/32) ad1.3 (lpc2138) 27:26 p0.13 0 0 gpio port 0.13 0 0 1 reserved (lpc2131/32) dtr (uart1) (lpc2138) 1 0 match 1.1 (timer 1) 1 1 reserved (lpc2131/32) ad1.4 (lpc2138) 29:28 p0.14 0 0 gpio port 0.14 0 0 1 reserved (lpc2131/32) dcd (uart1) (lpc2138) 1 0 eint1 1 1 sda1 (i 2 c1) 31:30 p0.15 0 0 gpio port 0.15 0 0 1 reserved (lpc2131/32) ri (uart1) (lpc2138) 1 0 eint2 1 1 reserved (lpc2131/32) ad1.5 (lpc2138) table 6: pin function select register 0 (pinsel0 - 0xe002c000) continued pinsel0 pin name value function value after reset
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 15 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 6.8 pin function select register 1 (pinsel1 - 0xe002c004) the pinsel1 register controls the functions of the pins as per the settings listed in t ab le 7 . the direction control bit in the iodir register is effective only when the gpio function is selected for a pin. for other functions direction is controlled automatically. settings other than those shown in the table are reserved, and should not be used. table 7: pin function select register 1 (pinsel1 - 0xe002c004) pinsel1 pin name value function value after reset 1:0 p0.16 0 0 gpio port 0.16 0 0 1 eint0 1 0 match 0.2 (timer 0) 1 1 capture 0.2 (timer 0) 3:2 p0.17 0 0 gpio port 0.17 0 0 1 capture 1.2 (timer 1) 1 0 sck (ssp) 1 1 match 1.2 (timer 1) 5:4 p0.18 0 0 gpio port 0.18 0 0 1 capture 1.3 (timer 1) 1 0 miso (ssp) 1 1 match 1.3 (timer 1) 7:6 p0.19 0 0 gpio port 0.19 0 0 1 match 1.2 (timer 1) 1 0 mosi (ssp) 1 1 capture 1.2 (timer 1) 9:8 p0.20 0 0 gpio port 0.20 0 0 1 match 1.3 (timer 1) 1 0 ssel (ssp) 1 1 eint3 11:10 p0.21 0 0 gpio port 0.21 0 0 1 pwm5 1 0 reserved (lpc2131/32) ad1.6 (lpc2138) 1 1 capture 1.3 (timer 1) 13:12 p0.22 0 0 gpio port 0.22 0 0 1 reserved (lpc2131/32) ad1.7 (lpc2138) 1 0 capture 0.0 (timer 0) 1 1 match 0.0 (timer 0) 15:14 p0.23 0 0 gpio port 0.23 0 0 1 reserved 1 0 reserved 1 1 reserved
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 16 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 6.9 pin function select register 2 (pinsel2 - 0xe002c014) the pinsel2 register controls the functions of the pins as per the settings listed in t ab le 8 . the direction control bit in the iodir register is effective only when the gpio function is selected for a pin. for other functions direction is controlled automatically. settings other than those shown in the table are reserved, and should not be used. 17:16 p0.24 0 0 reserved 0 0 1 reserved 1 0 reserved 1 1 reserved 19:18 p0.25 0 0 gpio port 0.25 0 0 1 ad0.4 1 0 reserved (lpc2131) aout (dac) (lpc2132/38) 1 1 reserved 21:20 p0.26 0 0 gpio port 0.26 0 0 1 ad0.5 1 0 reserved 1 1 reserved 23:22 p0.27 0 0 gpio port 0.27 0 0 1 ad0.0 1 0 capture 0.1 (timer 0) 1 1 match 0.1 (timer 0) 25:24 p0.28 0 0 gpio port 0.28 0 0 1 ad0.1 1 0 capture 0.2 (timer 0) 1 1 match 0.2 (timer 0) 27:26 p0.29 0 0 gpio port 0.29 0 0 1 ad0.2 1 0 capture 0.3 (timer 0) 1 1 match 0.3 (timer 0) 29:28 p0.30 0 0 gpio port 0.30 0 0 1 ad0.3 1 0 eint3 1 1 capture 0.0 (timer 0) 31:30 p0.31 0 0 gpio port 0 0 1 reserved 1 0 reserved 1 1 reserved table 7: pin function select register 1 (pinsel1 - 0xe002c004) continued pinsel1 pin name value function value after reset
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 17 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 6.10 general purpose parallel i/o device pins that are not connected to a speci?c peripheral function are controlled by the gpio registers. pins may be dynamically con?gured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back, as well as the current state of the port pins. 6.10.1 features ? direction control of individual bits. ? separate control of output set and clear. ? all i/o default to inputs after reset. 6.11 10-bit a/d converter the lpc2131/32 contain one and the lpc2138 contains two analog to digital converters. these converters are single 10-bit successive approximation analog to digital converters with eight multiplexed channels. 6.11.1 features ? measurement range of 0 v to 3.3 v. ? each converter capable of performing more than 400,000 10-bit samples per second. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition on input pin or timer match signal. ? global start command for both converters (lpc2138 only). 6.12 10-bit d/a converter this peripheral is available in the lpc2138 only. the d/a converter enables the lpc2138 to generate variable analog output. 6.12.1 features ? 10 bit digital to analog converter. ? buffered output. ? power-down mode available. ? selectable speed versus power. table 8: pin function select register 2 (pinsel2 - 0xe002c014) pinsel2 bits description reset value 1:0 reserved - 2 when 0, pins p1.31:26 are gpio pins. when 1, p1.31:26 are used as debug port. 0 3 when 0, pins p1.25:16 are used as gpio pins. when 1, p1.25:16 are used as trace port. 0 31:30 reserved -
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 18 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 6.13 uarts the lpc2131/2132/2138 each contain two uarts. in addition to standard transmit and receive data lines, the lpc2138 uart1 provides a full modem control handshake interface, too. 6.13.1 features ? 16 byte receive and transmit fifos. ? register locations conform to 550 industry standard. ? receiver fifo trigger points at 1, 4, 8, and 14 bytes ? built-in baud rate generator. ? standard modem interface signals included on uart1. (lpc2138 only) ? the lpc2131/2132/2138 transmission fifo control enables implementation of software (xon/xoff) ?ow control on both uarts and hardware (cts/rts) ?ow control on the lpc2138 uart1 only. 6.14 i 2 c-bus serial i/o controller the lpc2131/2132/2138 each contain two i 2 c-bus controllers. the i 2 c-bus is bi-directional, for inter-ic control using only two wires: a serial clock line (scl), and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver or a transmitter with the capability to both receive and send information (such as memory)). transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. the i 2 c-bus implemented in lpc2131/2132/2138 supports bit rates up to 400 kbit/s (fast i 2 c). 6.14.1 features ? standard i 2 c compliant bus interface. ? easy to con?gure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus may be used for test and diagnostic purposes.
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 19 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 6.15 spi serial i/o controller the lpc2131/2132/2138 each contain one spi controller. the spi is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. 6.15.1 features ? compliant with serial peripheral interface (spi) speci?cation. ? synchronous, serial, full duplex, communication. ? combined spi master and slave. ? maximum data bit rate of one eighth of the input clock rate. 6.16 ssp serial i/o controller the lpc2131/2132/2138 each contain one serial synchronous port controller (ssp). the ssp controller is capable of operation on a spi, 4-wire ssi?, or microwire? bus. it can interact with multiple masters and slaves on the bus. however, only a single master and a single slave can communicate on the bus during a given data transfer. the ssp supports full duplex transfers, with frames of 4 bits to 16 bits of data ?owing from the master to the slave and from the slave to the master. often only one of these data ?ows carries meaningful data. 6.16.1 features ? compatible with motorola spi, 4-wire ti ssi and national semiconductor microwire buses. ? synchronous serial communication. ? master or slave operation. ? 8-frame fifos for both transmit and receive. ? four bits to 16 bits per frame. 6.17 general purpose timers/counters the timer/counter is designed to count cycles of the peripheral clock (pclk) or an externally supplied clock, and optionally generate interrupts or perform other actions at speci?ed timer values, based on four match registers. it also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. multiple pins can be selected to perform a single capture or match function, providing an application with or and and, as well as broadcast functions among them. 6.17.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation. ? four 32-bit capture channels per timer that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt.
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 20 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers ? four 32-bit match registers that allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? four external outputs per timer corresponding to match registers, with the following capabilities: C set low on match. C set high on match. C toggle on match. C do nothing on match. 6.18 watchdog timer the purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. when enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time. 6.18.1 features ? internally resets chip if not periodically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 32-bit timer with internal pre-scaler. ? selectable time period from (t pclk 256 4) to (t pclk 2 32 4) in multiples of t pclk 4. 6.19 real-time clock the real-time clock (rtc) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. the rtc has been designed to use little power, making it suitable for battery powered systems where the cpu is not running continuously (idle mode). 6.19.1 features ? measures the passage of time to maintain a calendar and clock. ? ultra-low power design to support battery powered systems. ? provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? can use either the rtc dedicated 32 khz oscillator input or clock derived from the external crystal/oscillator input at xtal1. programmable reference clock divider allows ?ne adjustment of the rtc.
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 21 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers ? dedicated power supply pin can be connected to a battery or the main 3.3 v. 6.20 pulse width modulator the pwm is based on the standard timer block and inherits all of its features, although only the pwm function is pinned out on the lpc2131/2132/2138. the timer is designed to count cycles of the peripheral clock (pclk) and optionally generate interrupts or perform other actions when speci?ed timer values occur, based on seven match registers. the pwm function is also based on match register events. the ability to separately control rising and falling edge locations allows the pwm to be used for more applications. for instance, multi-phase motor control typically requires three non-overlapping pwm outputs with individual control of all three pulse widths and positions. two match registers can be used to provide a single edge controlled pwm output. one match register (mr0) controls the pwm cycle rate, by resetting the count upon match. the other match register controls the pwm edge position. additional single edge controlled pwm outputs require only one match register each, since the repetition rate is the same for all pwm outputs. multiple single edge controlled pwm outputs will all have a rising edge at the beginning of each pwm cycle, when an mr0 match occurs. three match registers can be used to provide a pwm output with both edges controlled. again, the mr0 match register controls the pwm cycle rate. the other match registers control the two pwm edge positions. additional double edge controlled pwm outputs require only two match registers each, since the repetition rate is the same for all pwm outputs. with double edge controlled pwm outputs, speci?c match registers control the rising and falling edge of the output. this allows both positive going pwm pulses (when the rising edge occurs prior to the falling edge), and negative going pwm pulses (when the falling edge occurs prior to the rising edge). 6.20.1 features ? seven match registers allow up to six single edge controlled or three double edge controlled pwm outputs, or a mix of both types. ? the match registers also allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? supports single edge controlled and/or double edge controlled pwm outputs. single edge controlled pwm outputs all go high at the beginning of each cycle unless the output is a constant low. double edge controlled pwm outputs can have either edge occur at any position within a cycle. this allows for both positive going and negative going pulses. ? pulse period and width can be any number of timer counts. this allows complete ?exibility in the trade-off between resolution and repetition rate. all pwm outputs will occur at the same repetition rate. ? double edge controlled pwm outputs can be programmed to be either positive going or negative going pulses.
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 22 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers ? match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. software must release new match values before they can become effective. ? may be used as a standard timer if the pwm mode is not enabled. ? a 32-bit timer/counter with a programmable 32-bit prescaler. 6.21 system control 6.21.1 crystal oscillator the oscillator supports crystals in the range of 10 mhz to 25 mhz. the oscillator output frequency is called f osc and the arm processor clock frequency is referred to as cclk for purposes of rate equations, etc. f osc and cclk are the same value unless the pll is running and connected. refer to section 6.21.2 pll for additional information. 6.21.2 pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up into the range of 10 mhz to 60 mhz with a current controlled oscillator (cco). the multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the cpu). the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is providing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. since the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle.the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must con?gure and activate the pll, wait for the pll to lock, then connect to the pll as a clock source. the pll settling time is 100 m s. 6.21.3 reset and wake-up timer reset has two sources on the lpc2131/2132/2138: the reset pin and watchdog reset. the reset pin is a schmitt trigger input pin with an additional glitch ?lter. assertion of chip reset by any source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a ?xed number of clocks have passed, and the on-chip flash controller has completed its initialization. when the internal reset is removed, the processor begins executing at address 0, which is the reset vector. at that point, all of the processor and peripheral registers have been initialized to predetermined values. the wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. this is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. since the oscillator and other functions are turned off during power-down mode, any wake-up of the processor from power-down mode makes use of the wake-up timer. the wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. when power is applied to the chip, or some event caused the chip to exit power-down mode, some time is required for the oscillator to produce a
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 23 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers signal of suf?cient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 6.21.4 brown-out detector the lpc2131/2132/2138 include 2-stage monitoring of the voltage on the v dd pins. if this voltage falls below 2.9 v, the bod asserts an interrupt signal to the vectored interrupt controller. this signal can be enabled for interrupt; if not, software can monitor the signal by reading dedicated register. the second stage of low-voltage detection asserts reset to inactivate the lpc2131/2132/2138 when the voltage on the v dd pins falls below 2.6 v. this reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. the bod circuit maintains this reset down below 1 v, at which point the por circuitry maintains the overall reset. both the 2.9 v and 2.6 v thresholds include some hysteresis. in normal operation, this hysteresis allows the 2.9 v detection to reliably interrupt, or a regularly-executed event loop to sense the condition. 6.21.5 code security this feature of the lpc2131/2132/2138 allow an application to control whether it can be debugged or protected from observation. if after reset on-chip boot-loader detects a valid checksum in flash and reads 0x87654321 from address 0x1fc in flash, debugging will be disabled and thus the code in flash will be protected from observation. once debugging is disabled, it can be enabled only by performing a full chip erase. 6.21.6 external interrupt inputs the lpc2131/2132/2138 include up to nine edge or level sensitive external interrupt inputs as selectable pin functions. when the pins are combined, external events can be processed as four independent interrupt signals. the external interrupt inputs can optionally be used to wake up the processor from power-down mode. 6.21.7 memory mapping control the memory mapping control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000. vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip static ram. this allows code running in different memory spaces to have control of the interrupts. 6.21.8 power control the lpc2131/2132/2138 support two reduced power modes: idle mode and power-down mode. in idle mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue operation during idle mode and may generate interrupts to cause the processor to resume execution. idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses.
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 24 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers in power-down mode, the oscillator is shut down and the chip receives no internal clocks. the processor state and registers, peripheral registers, and internal sram values are preserved throughout power-down mode and the logic levels of chip output pins remain static. the power-down mode can be terminated and normal operation resumed by either a reset or certain speci?c interrupts that are able to function without clocks. since all dynamic operation of the chip is suspended, power-down mode reduces chip power consumption to nearly zero. a power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. 6.21.9 vpb bus the vpb divider determines the relationship between the processor clock (cclk) and the clock used by peripheral devices (pclk). the vpb divider serves two purposes. the ?rst is to provide peripherals with the desired pclk via vpb bus so that they can operate at the speed chosen for the arm processor. in order to achieve this, the vpb bus may be slowed down to 1 2 to 1 4 of the processor clock rate. because the vpb bus must work properly at power-up (and its timing cannot be altered if it does not work since the vpb divider control registers reside on the vpb bus), the default condition at reset is for the vpb bus to run at 1 4 of the processor clock rate. the second purpose of the vpb divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. because the vpb divider is connected to the pll output, the pll remains active (if it was running) during idle mode. 6.22 emulation and debugging the lpc2131/2132/2138 support emulation and debugging via a jtag serial port. a trace port allows tracing program execution. debugging and trace functions are multiplexed only with gpios on port 1. this means that all communication, timer and interface peripherals residing on port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself. 6.22.1 embeddedice standard arm embeddedice logic provides on-chip debug support. the debugging of the target system requires a host computer running the debugger software and an embeddedice protocol convertor. embeddedice protocol convertor converts the remote debug protocol commands to the jtag data needed to access the arm core. the arm core has a debug communication channel function built-in. the debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program ?ow or even entering the debug state. the debug communication channel is accessed as a co-processor 14 by the program running on the arm7tdmi-s core. the debug communication channel allows the jtag port to be used for sending and receiving data without affecting the normal program ?ow. the debug communication channel data and control registers are mapped in to addresses in the embeddedice logic.
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 25 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 6.22.2 embedded trace since the lpc2131/2132/2138 have signi?cant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. the embedded trace macrocell? provides real-time trace capability for deeply embedded processor cores. it outputs information about processor execution to the trace port. the etm is connected directly to the arm core and not to the main amba system bus. it compresses the trace information and exports it through a narrow trace port. an external trace port analyzer must capture the trace information under software debugger control. instruction trace (or pc trace) shows the ?ow of execution of the processor and provides a list of all the instructions that were executed. instruction trace is signi?cantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. trace information generation can be controlled by selecting the trigger resource. trigger resources include address comparators, counters and sequencers. since trace information is compressed the software debugger requires a static image of the code being executed. self-modifying code can not be traced because of this restriction. 6.22.3 realmonitor realmonitor is a con?gurable software module, developed by arm inc., which enables real time debug. it is a lightweight debug monitor that runs in the background while users debug their foreground application. it communicates with the host using the dcc, which is present in the embeddedice logic. the lpc2131/2132/2138 contain a speci?c con?guration of realmonitor software programmed into the on-chip flash memory.
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 26 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 7. limiting values [1] the following applies to the limiting values: a) stresses above those listed under limiting values may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in section 8 static char acter istics and section 9 dynamic char acter istics of this speci?cation is not implied. b) this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. c) parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] only valid when the v dd supply voltage is present. [4] not to exceed 4.6 v. [5] the peak current is limited to 25 times the corresponding maximum current. [6] dependent on package type. table 9: limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage, core and external rail - 0.5 +3.6 v v dda analog 3.3 v pad supply voltage - 0.5 4.6 v v bat rtc power supply voltage - 0.5 4.6 v v ref a/d converter reference voltage - 0.5 4.6 v v ia analog input voltage on a/d related pins - 0.5 5.1 v v i dc input voltage, 5 v tolerant i/o pins [2] [3] - 0.5 6.0 v v i dc input voltage, other i/o pins [2] - 0.5 v dd + 0.5 [4] v i dd dc supply current per supply pin - 100 [5] ma i ss dc ground current per ground pin - 100 [5] ma t stg storage temperature [6] - 40 125 c p tot total power dissipation (based on package heat transfer, not device power consumption) - 1.5 w
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 27 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 8. static characteristics table 10: dc characteristics t a = - 40 c to +85 c for commercial, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit v dd supply voltage, core and external rail 3.0 3.3 3.6 v v dda analog 3.3 v pad supply voltage 2.5 3.3 3.6 v v bat rtc supply voltage 3.0 3.3 3.6 v v ref a/d converter reference voltage 3.0 3.3 3.6 v standard port pins, reset, rtck i il low-level input current v i = 0 v; no pull-up - - 3 m a i ih high-level input current v i =v dd ; no-pull-down - - 3 m a i oz 3-state output leakage current v o =0v, v o =v dd ; no pull-up/down --3 m a i latch i/o latch-up current - (0.5 v dd ) < v < (1.5 v dd ) t j < 125 c - - 100 ma v i input voltage [2] [3] [4] 0 - 5.5 v v o output voltage output active 0 - v dd v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage [5] i oh = - 4 ma v dd - 0.4 - - v v ol low-level output voltage [5] i ol = - 4 ma - - 0.4 v i oh high-level output current [5] v oh =v dd - 0.4 v - 4--ma i ol low-level output current [5] v ol = 0.4 v 4 - - ma i ohs high-level short circuit current [6] v oh =0 - - - 45 ma i ols low-level short circuit current [6] v ol =v dda - - 50 ma i pd pull-down current v i =5v [7] 10 50 150 m a i pu pull-up current (applies to p1.16 to p1.25) v i =0 - 15 - 50 - 85 m a v dd < v i < 5 v [7] 000 m a i dd active mode supply current v dd = 3.3 v, cclk = 60 mhz, t a =25 c, code while(1){} executed from flash, no active peripherals - - ma power-down mode v dd = 3.3 v, t a = +25 c, - - m a v dd = 3.3 v, t a = +85 c - m a i 2 c-bus pins v ih high-level input voltage v tol is from 4.5 v to 5.5 v 0.7v tol --v v il low-level input voltage v tol is from 4.5 v to 5.5 v - - 0.3v tol v
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 28 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers [1] typical ratings are not guaranteed. the values listed are at room temperature (+25 ?c), nominal supply voltages. [2] including voltage on outputs in 3-state mode. [3] v dd supply voltages must be present. [4] 3-state outputs go into 3-state mode when v dd is grounded. [5] accounts for 100 mv voltage drop in all supply lines. [6] only allowed for a short time period. [7] minimum condition for v i = 4.5 v, maximum condition for v i = 5.5 v. [1] conditions: v ssa =0v, v dda = 3.3 v. [2] the a/d is monotonic, there are no missing codes. [3] the differential non-linearity (e d ) is the difference between the actual step width and the ideal step width. see figure 4 . [4] the integral no-linearity (e l(adj) ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 4 . [5] the offset error (e o ) is the absolute difference between the straight line which ?ts the actual curve and the straight line which ?ts the ideal curve. see figure 4 . [6] the gain error (e g ) is the relative difference in percent between the straight line ?tting the actual transfer curve after removing offset error, and the straight line which ?ts the ideal transfer curve. see figure 4 . [7] the absolute voltage error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated a/d and the ideal transfer curve. see figure 4 . v hys hysteresis voltage v tol is from 4.5 v to 5.5 v - 0.5v tol -v v ol low-level output voltage [5] i ols = 3 ma - - 0.4 v i li input leakage current to v ss v i =v dd -24 m a v i =5v - 10 22 m a oscillator pins v xtal1 xtal1 input voltages 0 - 1.8 v v xtal2 xtal2 output voltages 0 - 1.8 v v rtxc1 rtxc1 input voltages 0 - 1.8 v v rtxc2 rtxc2 output voltages 0 - 1.8 v table 10: dc characteristics continued t a = - 40 c to +85 c for commercial, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit table 11: a/d converter dc electrical characteristics v dda = 2.5 v to 3.6 v unless otherwise speci?ed; t a = - 40 cto+85 c unless otherwise speci?ed; a/d converter frequency 4.5 mhz. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v c iss analog input capacitance -1pf e d differential non-linearity [1] [2] [3] - 1 lsb e l(adj) integral non-linearity [1] [4] - 2 lsb e o offset error [1] [5] - 3 lsb e g gain error [1] [6] - 0.5 % e t absolute error [1] [7] - 4 lsb
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 29 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential non-linearity (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 4. a/d conversion characteristics. 002aab136 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda - v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 30 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 9. dynamic characteristics [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] bus capacitance c b in pf, from 10 pf to 400 pf. table 12: ac characteristics t a =0 cto + 70 c for commercial, - 40 c to +85 c for industrial, v dd over speci?ed ranges [1] symbol parameter conditions min typ [1] max unit external clock f osc oscillator frequency 10 - 25 mhz t clk oscillator clock period 40 - 100 ns t chcx clock high time t clk 0.4 - - ns t clcx clock low time t clk 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns port pins (except p0.2 and p0.3) t r(o) output rise time - 10 - ns t f(o) output fall time - 10 - ns i 2 c-bus pins (p0.2 and p0.3) t of output fall time v ih to v il 20 + 0.1 c b [2] --ns
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 31 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 9.1 timing fig 5. external clock timing. t chcl t clcx t chcx t clk t clch 002aab137 0.2v dd + 0.9 0.2v dd - 0.1 v v dd - 0.5 v 0.45 v
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 32 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 10. package outline fig 6. package outline sot314-2 (lqfp64). unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 33 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 11. abbreviations table 13: acronym list acronym description adc analog-to-digital converter bod brown-out detection cpu central processing unit dac digital-to-analog converter dcc debug communications channel fifo first in, first out gpio general purpose input/output pll phase-locked loop por power-on reset pwm pulse width modulator ram random access memory sram static random access memory uart universal asynchronous receiver/transmitter vic vector interrupt controller vpb vlsi peripheral bus
9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 34 of 36 philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 12. revision history table 14: revision history document id release date data sheet status change notice doc. number supersedes lpc2131_2132_2138 _1 20041118 preliminary data sheet - 9397 750 14008 -
philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 9397 750 14008 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data sheet rev. 01 18 november 2004 35 of 36 13. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 14. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 15. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 16. licenses 17. trademarks arm is a registered trademark of arm, inc. arm7tdmi-s is a trademark of arm, inc. embeddedice is a registered trademark of arm, inc. embedded trace macrocell is a trademark of arm, inc. microwire is a trademark of national semiconductors, inc. realmonitor is a trademark of arm, inc. spi is a trademark of motorola, inc. ssi is a trademark of texas instruments, inc. thumb is a registered trademark of arm, inc. 18. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). purchase of philips i 2 c-bus components purchase of philips i 2 c-bus components conveys a license under the philips i 2 c-bus patent to use the components in the i 2 c-bus system provided the system conforms to the i 2 c-bus speci?cation de?ned by koninklijke philips electronics n.v. this speci?cation can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 18 november 2004 document number: 9397 750 14008 published in the u.s.a. philips semiconductors lpc2131/2132/2138 single-chip 16/32-bit microcontrollers 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 9 6.1 architectural overview. . . . . . . . . . . . . . . . . . . . 9 6.2 on-chip flash program memory . . . . . . . . . . . 9 6.3 on-chip static ram . . . . . . . . . . . . . . . . . . . . . 9 6.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . 10 6.6 pin connect block . . . . . . . . . . . . . . . . . . . . . . 12 6.7 pin function select register 0 (pinsel0 - 0xe002c000) . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.8 pin function select register 1 (pinsel1 - 0xe002c004) . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.9 pin function select register 2 (pinsel2 - 0xe002c014) . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.10 general purpose parallel i/o. . . . . . . . . . . . . . 17 6.11 10-bit a/d converter . . . . . . . . . . . . . . . . . . . . 17 6.12 10-bit d/a converter . . . . . . . . . . . . . . . . . . . . 17 6.13 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.14 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 18 6.15 spi serial i/o controller. . . . . . . . . . . . . . . . . . 19 6.16 ssp serial i/o controller . . . . . . . . . . . . . . . . . 19 6.17 general purpose timers/counters . . . . . . . . . . 19 6.18 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 20 6.19 real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 20 6.20 pulse width modulator . . . . . . . . . . . . . . . . . . 21 6.21 system control . . . . . . . . . . . . . . . . . . . . . . . . 22 6.22 emulation and debugging . . . . . . . . . . . . . . . . 24 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 8 static characteristics. . . . . . . . . . . . . . . . . . . . 27 9 dynamic characteristics . . . . . . . . . . . . . . . . . 30 9.1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 package outline . . . . . . . . . . . . . . . . . . . . . . . . 32 11 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . 34 13 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 35 14 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 15 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 16 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 18 contact information . . . . . . . . . . . . . . . . . . . . 35

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